(1) Technical Field
This invention relates to a wafer orienting apparatus. More particularly, this invention relates to a wafer orienting apparatus for wafers having a notch on a periphery using mechanical motion only.
(2) Description of the Prior Art
The following six documents relate to apparatus dealing with positioning a notch or flat on a periphery of a semiconductor wafer to identify its orientation.
U.S. Pat. No. 4,970,772 issued Nov. 20, 1990 to Robert E. Steere, III shows a method for aligning semiconductor wafers in a wafer cassette by providing an alignment fixture for wafers having a notch in a periphery.
U.S. Pat. No. 5,205,028 issued Apr. 27, 1993 to Thomas E. Leonard describes a method which can align notched wafers and/or align wafers with flats with one another.
U.S. Pat. No. 5,516,732 issued May 14, 1996 to Christopher Fleggal describes a method of pre and post handling and treatment of wafers in a vacuum between wafer cassette modules and a multistation wafer processing machine.
U.S. Pat. No. 5,533,243 issued Jul. 9, 1996 to Takanobu Asano describes a notch position aligning device with a rotating/supporting mechanism to align a plurality of wafers in a predetermined direction and minimize contact between the target and other members.
U.S. Pat. No. 5,551,829 issued Sep. 3, 1996 to Mark J. Jerolimov et describes an orientation apparatus and method for aligning indexing notches of disk-shaped members, such as semiconductor wafers, with a flexible, non-particulating alignment rod which rotates until the indexing notches are registered with the alignment rod.
U.S. Pat. No. 5,662,452 issued Sep. 2, 1997 to Quincy D. Allison describes an apparatus and method for aligning indexing notches of disk-shaped members, such as semiconductor wafers, using friction between the circumferential surfaces of an alignment rod and the drive roller.
During various stages of semiconductor wafer processing, precise positioning of a wafer is critical. For example, a fabrication step that includes ion implantation requires that the orientation of the crystalline lattice of the semiconductor material be known. For another example, there must be a precise alignment of a semiconductor wafer relative to a reticle or photomask, if the reticule or photomask is to be used to pattern a conductive layer for forming signal paths along a previously fabricated circuit structure on the wafer.
Various types of cassettes have been provided for conveying a plurality of wafers, such as semiconductor silicon wafers, from one place to another. Wafers are formed with a notch in the periphery for identification purposes and subsequent alignment and other operations. In order to align such wafers in a cassette, it has been known to use a wafer orienting apparatus. The apparatus usually includes a cassette support means to receive a cassette containing a row of wafers as well as a roller to lift the wafers within the cassette and to rotate the wafers until the notch in each wafer comes into alignrnent (usually with a steel rod) and drops down.
Referring to FIG. 1, typically, a semiconductor wafer 10 will include both a wafer flat and an indexing notch 12 for positioning. A wafer flat or indexing notch 12 is an edge feature and is used to identify the orientation of the wafer 10. There are devices designed to align the flats of wafers 10, as well as "notch finders," devices which align the notches 12 of a semiconductor wafer 10 contained within a cassette 15.
Referring to FIG. 2, a schematic representation of the prior art showing the semiconductor wafers 10 with notched peripheries 12 in position in the cassette 15 with a pair of curvilinear walls which are sized to seat a wafer in an upstanding manner. FIG. 2 also shows the prior art rotating stainless steel rod 14, which acts as an aligning roller.
Referring now more particularly to FIG. 2 of the prior art, the notch finder may have a small diameter stainless steel rod 14 having a coating of polyvinlydenefloride. When the cassette 15 is positioned on the device, the edges of the wafer in the cassette 15 contact the stainless steel rod 14. Rotation of the stainless steel rod 14 causes the wafers 10 to rotate within the cassette 15. When a notch 12 of a rotating wafer 10 reaches the stainless steel rod 14, the notch 12 allows for the wafer 10 to drop slightly onto the rod 14. The stainless steel rod 14 continues to rotate, but the notchto-rod registration prevents further rotation of the wafer 10. Within a relatively short time, all of the wafers 10 in the cassette 15 have been aligned.
In the prior art of FIG. 2, once the wafer 10 has been placed in the cassette 15, a minimum of time and effort is required to bring about an alignment of the notches 12 of the respective wafers 10 in the cassette 15. The cassette 15 is of conventional structure. The wafer 10 is rotated by the rotating stainless steel rod 14 until the notched periphery 12 comes in contact with the rod 14, falling down into alignment and ceasing to rotate
A notch finder may also include a mechanism for uniformly rotating the wafer notches after an alignment operation. Rollers may be positioned on opposite sides of the stainless steel rod out of contact with the wafers during the notch alignment operation. Then, the rollers may be moved upwardly to contact the wafer edges, lifting the notch away from the stainless steel rod. The rollers can then be rotated to relocate the aligned notches to a desired position.
Conventional notch finders operate well for their intended purpose. However, there are concerns relating to the operation of the conventional notch finders. As previously noted, the stainless steel rod continues to rotate after the first notch is brought into registration with the rod. Rotation of the stainless steel rod against the stationary edges of the notch generates noises that can be disruptive to persons in the vicinity of the notch finder. More importantly, the relative rotation between the stainless steel rod and the semiconductor wafer may generate particles that settle on the surface of one or more of the wafers. Particulate contamination will adversely affect the manufacturing throughput of the semiconductor fabrication process.